1. Technical Field of the Invention
The present invention generally relates to semiconductor memory devices and, more particularly, to an interleaved sense amplifier with a single sided precharge device which provides for simplification, as well as a reduction in the area of occupation, of conventional sense amplifier circuitry, thereby resulting in chip size reduction.
2. Description of the Related Art
Currently, many dynamic semiconductor memory devices such as dynamic random access memory (DRAM) utilize folded bit line, interleaved sense amplifier arrangements, whereby two sets of paired bit lines (from a plurality of paired bit lines) are coupled to, and share a single sense amplifier. Referring to FIG. 1, a circuit diagram is shown of a representative portion in a DRAM of a configuration for a conventional interleaved sense amplifier. In general, each bit line pair ("BL") includes a bit line true ("BLt") and a bit line complement ("BLc"), the BLt and BLc each being connected to a plurality of dynamic memory cells (not shown) in a memory array (not shown) comprising the DRAM. As is known in the art, each memory cell includes a capacitor (not shown) for storing a charge which indicates whether the cell is in a logic "1" or logic "0" state. The charge associated with a given memory cell may be coupled onto its corresponding bit line when addressed by a wordline connected to the memory cell.
The illustrated portion of FIG. 1 has four pairs of bit lines identified as BLta(0) BLca(0)-(the "upper left bit line pair"), BLta(2)-BLca(2) (the "lower left bit line pair"), BLtb(0)-Blcb(0) (the "upper right bit line pair"), and BLtb(2)-Blcb(2) (the "lower right bit line pair"). The upper left bit line pair is coupled to one side of a sense amplifier S1 via isolation transistors T4 and T5. The upper right bit line pair is coupled to the other side of sense amplifier S1 via isolation transistors T12 and T13. Similarly, the lower left bit line pair is coupled to one side of a sense amplifier S2 via isolation transistors T23 and T24 and the lower right bit line pair is coupled to the other side of sense amplifier S2 via isolation transistors T31 and T32. The gates of isolation transistor pairs T4, T5 and T23, T24 are connected to a MUXa signal line and the gates of isolation transistor pairs T12, T13 and T31, T32 are connected to a MUXb signal line. In response to a MUXa signal, isolation transistors T4 and T5 are energized to couple the upper left bit line pair to the sense amplifier S1, and isolation transistors T23 and T24 are energized to couple the lower left bit line pair to the sense amplifier S2. Likewise, a MUXb signal causes isolation transistors T12 and T13 to couple the upper right bit line pair to sense amplifier S1 and isolation transistors T31 and T32 to couple the lower right bit line pair to the sense amplifier S2.
The sense amplifiers S1 and S2 each include an N-Sense cross-coupled latch (i.e., transistors T8 and T9 in S1 and transistors T27 and T28 in S2) and a P-Sense cross-coupled latch (i.e., transistors T10 and T11 in S1 and transistors T29 and T30 in S2). The N-sense latches operate in response to an NCS signal and the P-sense latches operate in response to a PCS signal, which causes each of the sense amplifiers to sense and amplify a potential difference between a selected one of the bit lines pairs (i.e., sense amplifier nodes SAt(0) and SAc(0) for S1 and nodes SAt(2) and SAc(2) for S2). In addition, each sense amplifier includes a bit switch, i.e., transistors T6 and T7 for S1 and transistors T25 and T26 for S2, which is used for coupling the sense amplifier S1 nodes to local data lines LDQt(0) and LDQc(0) and sense amplifier S2 nodes to local data lines LDQt(2) and LDQc(2), respectively, in response to a CSL (column select) signal.
The circuit of FIG. 1 includes four precharge devices P1, P2, P3 and P4. The precharge device P1 (consisting of precharging transistors T1 and T3 and an equalization transistor T3) is connected between the upper left bit line pair (BLta(0) and BLca(0)) and operates by shorting the upper left bit line pair together and then precharging the pair to a common voltage level during an equalization/precharge operation. The precharge device P2 (consisting of precharging transistors T14 and T15 and an equalization transistor T16) is connected between the upper right bit line pair (BLtb(0) and BLcb(0)) and, likewise, operates by shorting the upper right bit line pair together and precharging the pair to a common voltage level during the equalization/precharge operation. The precharge devices P3 (transistors T17, T18 and T19) and P4 (transistors T20, T21 and T22) are connected between the lower left bit line pair and lower right bit line pair, respectively, and operate in a similar manner as discussed above for precharge devices P1 and P2. The equalization transistors T3 and T19 are responsive to equalization signal EQLa and transistors T16 and T20 are responsive to equalization signal EQLb.
A leakage limiter device LL1 is operatively coupled to precharge devices P1 and P3 for limiting the precharge current supplied by a voltage source VBLEQ during the equalization/precharge operation. Likewise, a leakage limiter device LL2 is operatively coupled to precharge devices P2 and P4 for limiting the precharge current supplied by the voltage source VBLEQ during the equalization/precharge operation. Moreover, in the event of a wordline--bitline short whereby a current path is formed from the grounded wordline through the short to the bitline and then from the bitline through a corresponding precharge device to the VBELQ precharge net (i.e., the wiring that supplies the precharge voltage VBELQ to all the sense amplifiers on the chip), the leakage limiter device adds resistance in the path between the corresponding precharge device and the VBELQ precharge net. Consequently, the flow of standby leakage current resulting from each wordline--bitline short is limited by the resistance provided by the leakage limiter device that is located in the path between the precharge device and VBELQ precharge net.
The circuit of FIG. 1 generally operates as follows. Assume that during a read operation, data from a selected memory cell (not shown) in the memory array (not shown) is coupled to one of the bit lines of the upper left bit line pair, i.e., BLta(0) and BLca(0). Prior to the read operation, an equalization/precharge operation is performed to short the BLta(0) and BLca(0) bit lines together and charge them to a common voltage level. The precharge voltage VBELQ is coupled to the precharge device P1 via the leakage limiter device LL1 which, as stated above, provides resistance to limit the amount of charging current supplied by the VBELQ net for bringing the upper left bit line pair to the common voltage. Subsequently, during the read operation, charge from the memory cell is coupled to the corresponding bit line which causes the common voltage on that bit line to be altered. The sense amplifier S1 then operates to amplify the potential difference between the upper left bit line pair, amplify the signal flowing in either the BLta(0) or BLca(0) (whichever one was altered from the transfer of charge between the memory cell) and then restore the charge to the associated memory cell before the read operation is complete In general, large capacity DRAM chips contain a significant amount of sense amplifiers which occupy space on the surface of the chips. With the demand for higher capacity memory chips, however, it has become increasingly important to conserve and utilize the available chip surface area as efficiently as possible. As shown in FIG. 1, each of the four bit line pairs has a precharge device and a leakage limiter device associated therewith and, consequently, each sense amplifier S1 and S2 has two precharge devices associated therewith. In addition, the leakage limiter devices LL1 and LL2 in FIG. 1 are generally implemented as depletion NFETs or enhancement NFETs. In comparison, depletion NFETs have better electrical properties and a relatively smaller layout size than enhancement NFETs, but require an additional channel implant process which increases the manufacturing cost to make them. Moreover, enhancement NFETs require a long channel to increase the resistance which results in a large layout size. Consequently, the area which is occupied by the precharge devices for each of the sense amplifiers and their associated leakage limiting devices significantly contributes to the chip area, as well as increased manufacturing costs of the DRAM. Accordingly, by reducing the size of the sense amplifier and it associated circuity and/or reducing the number of constituent or associated elements of the sense amplifier, a significantly smaller chip size can be realized.